Why i2c is used

Does the target device, in my case, a memory ic, an eeprom of 25 series, have a fixed address, or is given one? Pls help me out. Nice Article about I2C communication, I have used it in my college time. Its very helpful for my metro project. But explanation says the opposite. Am I not reading the signals correctly.

Could you please explain it. Read the signal from right to left. In this article, the waveforms are shown in the opposite sense that you would see on an oscilloscope. I had the same issue. Your email address will not be published. Save my name, email, and website in this browser for the next time I comment. Notify me of follow-up comments by email. Notify me of new posts by email. I agree to these terms.

Related Posts. Great series of posts. Thanks for sharing this! Thanks for this,u are a genius,i need simple circuit for invater and power Bank circuit Reply. Dani on February 22, at am. Thank you for taking the time to explain it so well Reply. Sachin Gupta on February 24, at am.

Thanks very nice information. I liked all your articles and the way you explained all. Please add for PCIe communication as well. Manuel Antonio Nava on March 30, at pm. Simple and easy to understand. I suggest some example to put in practice Reply.

Phil Howard on July 3, at am. Mitek on July 4, at am. Nigel on July 5, at am. Great post. Thank you very much!! RAVI on November 22, at pm. Please share CAN article also Reply. Bri on August 19, at pm. ArchonOSX on December 18, at pm. Circuit Basics on March 24, at am. Otherwise good articles and helpful explanations. Thanks for the work. Hello World on February 2, at pm. Like the Serial Peripheral Interface SPI , it is only intended for short distance communications within a single device.

To figure out why one might want to communicate over I 2 C, you must first compare it to the other available options to see how it differs. Because serial ports are asynchronous no clock data is transmitted , devices using them must agree ahead of time on a data rate. The two devices must also have clocks that are close to the same rate, and will remain so--excessive differences between clock rates on either end will cause garbled data.

Asynchronous serial ports require hardware overhead--the UART at either end is relatively complex and difficult to accurately implement in software if necessary. At least one start and stop bit is a part of each frame of data, meaning that 10 bits of transmission time are required for each 8 bits of data sent, which eats into the data rate.

Another core fault in asynchronous serial ports is that they are inherently suited to communications between two, and only two, devices. While it is possible to connect multiple devices to a single serial port, bus contention where two devices attempt to drive the same line at the same time is always an issue and must be dealt with carefully to prevent damage to the devices in question, usually through external hardware.

Finally, data rate is an issue. While there is no theoretical limit to asynchronous serial communications, most UART devices only support a certain set of fixed baud rates, and the highest of these is usually around bits per second. The most obvious drawback of SPI is the number of pins required. The rapid proliferation of pin connections makes it undesirable in situations where lots of devices must be connected to one controller.

Also, the large number of connections for each device can make routing signals more difficult in tight PCB layout situations. SPI only allows one controller on the bus, but it does support an arbitrary number of peripherals subject only to the drive capability of the devices connected to the bus and the number of chip select pins available.

SPI is good for high data rate full-duplex simultaneous sending and receiving of data connections, supporting clock rates upwards of 10MHz and thus, 10 million bits per second for some devices, and the speed scales nicely. The hardware at either end is usually a very simple shift register, allowing easy implementation in software. I 2 C requires a mere two wires, like asynchronous serial, but those two wires can support up to peripheral devices.

Also, unlike SPI, I 2 C can support a multi-controller system, allowing more than one controller [1] to communicate with all peripheral [1] devices on the bus although the controller devices can't talk to each other over the bus and must take turns using the bus lines. The hardware required to implement I 2 C is more complex than SPI, but less than asynchronous serial.

It can be fairly trivially implemented in software. I 2 C was originally developed in by Philips for various Philips chips. The original spec allowed for only kHz communications, and provided only for 7-bit addresses, limiting the number of devices on the bus to there are several reserved addresses, which will never be used for valid I 2 C addresses.

In , the first public specification was published, adding a kHz fast-mode as well as an expanded bit address space. Much of the time for instance, in the ATMega device on many Arduino-compatible boards , device support for I 2 C ends at this point.

There are three additional modes specified:. SMBus is a more tightly controlled format, intended to maximize predictability of communications between support ICs on PC motherboards. SMBus includes a clock timeout mode which makes low-speed operations illegal, although many SMBus devices will support it anyway to maximize interoperability with embedded I 2 C systems. The clock signal is always generated by the current bus controller; some peripheral devices may force the clock low at times to delay the controller sending more data or to require more time to prepare data before the controller attempts to clock it out.

This is called " clock stretching " and is described on the protocol page. Thus, there can be no bus contention where one device is trying to drive the line high while another tries to pull it low, eliminating the potential for damage to the drivers or excessive power dissipation in the system. Each signal line has a pull-up resistor on it, to restore the signal to high when no device is asserting it low. Notice the two pull-up resistors on the two communication lines. Resistor selection varies with devices on the bus, but a good rule of thumb is to start with 4.

I 2 C is a fairly robust protocol, and can be used with short runs of wire m. For long runs, or systems with lots of devices, smaller resistors are better. The SDL and SCL pins of the master device are designed with the transistors in open state, so data transfer is possible only when these transistors are conducted. Hence, these lines or drain terminals are connected thorough pull-up resistors to VCC for conduction mode.

Many slave devices are interfaced to the microcontroller with the help of the I2C bus through I2C level shifter IC for transferring the information between them. The I2C protocol used to connect a maximum of devices that are all connected to communicate with the SCL and SDL lines of the master unit as well as the slave devices.

It supports Multimaster communication, which means two masters are used to communicate the external devices. The I2C protocol operates three modes such as: fast mode, high-speed mode and standard mode wherein the standard mode data speed ranges 0Hz to Hz, and the fast mode data can transfer with 0Hz to KHz speed and the high speed mode with 10 KHz to KHz.

The 9-bit data is sent for each transfer wherein 8-bits are sent by the transmitter MSB to LSB, and the 9th bit is an acknowledgement bit sent by the receiver.

The number of slave devices is connected to the master device with the help of the I2C bus, wherein each slave consists of a unique address to communicate it. The following steps are used to communicate the master device to the slave:. Step1: First, the master device issues a start condition to inform all the slave devices so that they listen on the serial data line. If anyone address matches, that device is selected, and the remaining all devices are disconnected from the SCL and SDL lines.

Step3: The slave device with a matched address received from the master, responds with an acknowledgement to the master thereafter communication is established between both the master and slave devices on the data bus.

Step4: Both the master and slave receive and transmit the data depending on whether the communication is read or write. Step5: Then, the master can transmit 8-bit of data to the receiver which replies with a 1-bit acknowledgement. The most important I2C limitations include:. I2C is a great option for applications that require low cost and simple implementation rather than high speed.

For example, common uses of the I2C communication protocol include:. Actively scan device characteristics for identification. Use precise geolocation data. Select personalised content. Create a personalised content profile. Measure ad performance. Select basic ads. Create a personalised ads profile. Select personalised ads. Apply market research to generate audience insights. Measure content performance.